This invention relates to systems, computer-implemented methods, and computer program products for verification of Hardware Descriptor Language (HDL) hardware models.
Before this invention, it was a common challenge in the field of hardware verification to efficiently detect and react to the negative effects of a constantly evolving simulation code and logic design base. The existing methodology involves human monitoring of regression buckets for failing test runs; however, the sheer volume of data makes it very difficult to analyze every testcase in the context of past behavior. As a result, there is often a lag between when a testcase starts failing and when it is identified as having incurred breakage, and by that time it is much more difficult to isolate the root cause because more hardware and code changes have been promoted. Moreover, once the problem has been identified, a manual process of backing out the offending code and/or logic is both time-consuming and error-prone. Automating both of these processes allows the verification engineer to focus on the primary goal of identifying hardware bugs and also promotes an efficient environment in which to do so.